EPFL scientist are among the leaders in the race to develop an industry-ready prototype of a 3D chip as well as a high-performance and reliable manufacturing method. The chip is composed of three or more processors that are stacked vertically and connected together—resulting in increased speed and multitasking, more memory and calculating power, better functionality and wireless connectivity. Developed at the Microelectronics Systems Laboratory (LSM), Director Yusuf Leblebici is unveiling these results to experts on Wednesday the 25th of January in Paris, in a keynote presentation at the 2012 Interconnection Network Architectures Workshop.
